Difference between revisions of "BayHac2017/Clash"

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|Functional hardware description language
  
|Functional hardware description language
 
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|CλaSH Liaison:
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== What is CλaSH ==
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TODO: information on dependencies, testing, etc.
  
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CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.
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Features of CλaSH:
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  +
* Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
  +
* Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
  +
* Compile your designs for fast simulation.
  +
* Higher-order functions, in combination with type inference, result in designs that are fully parametric by default.
  +
* Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
  +
* Multiple clock domains, with type safe clock domain crossing.
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* Template language for introducing new VHDL/(System)Verilog primitives.
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  +
From the CλaSH website http://www.clash-lang.org/
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== CλaSH Project Ideas ==
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Christiaan Baaij, one of the principle creators of CλaSH gave these ideas for hackathon projects:
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* Building a small CPU is always fun I. Perhaps build one that can do: http://icfpc2011.blogspot.nl/2011/06/task-description-contest-starts-now.html?m=1
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* Or set it to dim lights that show the slowly diminishing state of each of the processors memory.
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* Or if you don't have enough leds, make a small vga driver (most forgiving display protocol)
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A project that I'm think about is:
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* To get a decent build system for CλaSH that includes regression testing with a verilog simulator and calling the appropriate EDA tools from either Altera or Xilinx to synthesize, place and route and then download the bitfile to the FPGA itself. A good starting point for this is the build system that Austin Seipp created in his claap project. You can find this build system inside of his project at https://github.com/thoughtpolice/claap.
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== Good FPGA Boards to Bring to BayHac2017 CλaSH Hackathon ==
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I will bring a few DE0-nano boards to the hackathon. They are quite inexpensive and can be purchased for about $85 on DigiKey https://www.digikey.com/products/en?mpart=P0082&v=771, adafruit https://www.adafruit.com/products/451 and other locations on the web.
  +
  +
A good list of boards can be found here: https://www.reddit.com/r/haskell/comments/5opec9/haskell_to_hardware_project_clash_701_released/
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  +
The list is copied here (thanks goes to darchon on the subreddit for haskell):
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* DE1-SoC (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=836)
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* SoCKit (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=167&No=816)
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* DE0-nano (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=139&No=593)
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* DE1 (http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=53&No=83)

Latest revision as of 18:18, 4 April 2017

Project: CλaSH
Description: Functional hardware description language
CλaSH Liaison: Richard Tobias
Source: https://github.com/clash-lang/clash-compiler
Website: http://www.clash-lang.org/

What is CλaSH

CλaSH (pronounced ‘clash’) is a functional hardware description language that borrows both its syntax and semantics from the functional programming language Haskell. It provides a familiar structural design approach to both combinational and synchronous sequential circuits. The CλaSH compiler transforms these high-level descriptions to low-level synthesizable VHDL, Verilog, or SystemVerilog.

Features of CλaSH:

  • Strongly typed, but with a very high degree of type inference, enabling both safe and fast prototyping using concise descriptions.
  • Interactive REPL: load your designs in an interpreter and easily test all your component without needing to setup a test bench.
  • Compile your designs for fast simulation.
  • Higher-order functions, in combination with type inference, result in designs that are fully parametric by default.
  • Synchronous sequential circuit design based on streams of values, called Signals, lead to natural descriptions of feedback loops.
  • Multiple clock domains, with type safe clock domain crossing.
  • Template language for introducing new VHDL/(System)Verilog primitives.

From the CλaSH website http://www.clash-lang.org/

CλaSH Project Ideas

Christiaan Baaij, one of the principle creators of CλaSH gave these ideas for hackathon projects:

A project that I'm think about is:

  • To get a decent build system for CλaSH that includes regression testing with a verilog simulator and calling the appropriate EDA tools from either Altera or Xilinx to synthesize, place and route and then download the bitfile to the FPGA itself. A good starting point for this is the build system that Austin Seipp created in his claap project. You can find this build system inside of his project at https://github.com/thoughtpolice/claap.

Good FPGA Boards to Bring to BayHac2017 CλaSH Hackathon

I will bring a few DE0-nano boards to the hackathon. They are quite inexpensive and can be purchased for about $85 on DigiKey https://www.digikey.com/products/en?mpart=P0082&v=771, adafruit https://www.adafruit.com/products/451 and other locations on the web.

A good list of boards can be found here: https://www.reddit.com/r/haskell/comments/5opec9/haskell_to_hardware_project_clash_701_released/

The list is copied here (thanks goes to darchon on the subreddit for haskell):

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